--
-- VHDL Architecture vga_lib.vsync.arch
--
-- Created:
--          by - andax656.student (southfork-12.edu.isy.liu.se)
--          at - 10:25:25 10/05/11
--
-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.numeric_std.all;

ENTITY vsync IS
   PORT( 
      fpga_clk     : IN     std_logic;
      fpga_reset_n : IN     std_logic;
      vga_clk      : IN     std_logic;
      vblank       : OUT    std_logic;
      vga_vsync_n  : OUT    std_logic;
      lcnt         : IN     integer RANGE 0 TO 525
   );

-- Declarations

END vsync ;

--
ARCHITECTURE arch OF vsync IS
BEGIN
  process(fpga_clk)
  begin
    if rising_edge(fpga_clk) then
    
      if fpga_reset_n = '0' then
        vga_vsync_n <= '1';
        
      elsif vga_clk = '1' then
      -- runs every 0,04 us
      
        if lcnt <= 490 then
          vga_vsync_n <= '1';
        elsif lcnt <= 492 then
          vga_vsync_n <= '0';
        else
          vga_vsync_n <= '1';
        end if;
      
        
        if lcnt <= 480 then
          vblank <= '0';
        else
          vblank <= '1';
        end if;
          
      end if;
    end if;
  end process;
END ARCHITECTURE arch;

